The present invention relates generally to the design of integrated circuits (ICs), and, more particularly, to methods for placing and routing metal lines in the ICs.
A modern ultra-large scale integration (ULSI) chip may contain millions of transistors that makes manual layout of such large chips too time consuming to be practical. With the large sizes of modern designs, this operation is usually performed by electronic design automation (EDA) tools. An EDA tool takes in circuit descriptions, places sub-blocks in the design areas and routes, i.e., interconnects the sub-blocks. Metal layers are typically used for such interconnections. Traditionally, each metal layer receives one routing pitch defined by a design rule's minimum width and space in a technology file. The EDA tool routes the metals lines according to the routing pitch. The minimum space is often limited by a score of factors, some are process related, and some are electrical. Leakage under a certain voltage between two adjacent metal lines is one of the electrical limitations. Especially when low-K dielectric material is used, the leakage becomes even more sensitive to the metal spacing.
In many chip designs, different voltages may be used in different parts of a chip. For example, a core area and a peripheral area in a memory chip may use different voltages. Sometimes these different voltages may be routed on the same metal layer.
FIG. 1 illustrates a conventional metal layer layout with one spacing rule but two voltages. Three adjacent metal lines 110, 120 and 130 are coupled to different voltage sources. Spaces between these metal lines are uniformly at S0 routed by traditional EDA tools. A potential difference between metal lines 110 and 120 is V0. A potential difference between metal lines 130 and 120 is V1. V1 is higher than V0. For instance, V0=1.0V, and V1=1.8V. In this case, the metal lines 110, 120 and 130 may be connected to a core area high voltage supply Vcc, a ground and a peripheral high voltage supply Vdd, respectively. While the space S0 is sufficient for V0, V1 it may cause excessive leakage between the metal lines 120 and 130.
As such, what is desired is an EDA method for routing metal lines with different spaces according to voltages the metal lines carry.